32 search results - page 2 / 7 » Non-cycle-accurate sequential equivalence checking |
FMCAD
2008
Springer
13 years 7 months ago
2008
Springer
Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimization...
ASPDAC
2009
ACM
13 years 10 months ago
2009
ACM
Iterative retiming and resynthesis is a powerful way to optimize sequential circuits but its massive adoption has been hampered by the hardness of verification. This paper tackle...
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
Retiming and resynthesis are among the most important techniques for practical sequential circuit optimization. However, their applicability is much limited due to verification c...
FMCAD
2009
Springer
14 years 10 days ago
2009
Springer
—Sequential equivalence checking (SEC) technologies, capable of demonstrating the behavioral equivalence of two designs, have grown dramatically in capacity over the past decades...
DAC
2012
ACM
11 years 8 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...