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» Non-local Instruction Scheduling with Limited Code Growth
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EUROSYS
2010
ACM
14 years 2 months ago
A Comprehensive Scheduler for Asymmetric Multicore Systems
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architect...
Juan Carlos Saez, Manuel Prieto Matias, Alexandra ...
ICDCSW
2008
IEEE
13 years 12 months ago
Fast Link Assessment in Wireless Mesh Networks by Using Non-Constant Weight Code
Abstract— The wireless mesh network is experiencing tremendous growth with the standardization of IEEE 802.11 and IEEE 802.16 technologies. Compared to its wired counterpart, the...
Ravi Nelavelli, Rajesh Prasad, Hongyi Wu
IEEEPACT
2000
IEEE
13 years 10 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
EGH
2005
Springer
13 years 11 months ago
Optimal automatic multi-pass shader partitioning by dynamic programming
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
Alan Heirich
IPPS
2007
IEEE
13 years 11 months ago
Optimizing Sorting with Machine Learning Algorithms
The growing complexity of modern processors has made the development of highly efficient code increasingly difficult. Manually developing highly efficient code is usually expen...
Xiaoming Li, María Jesús Garzar&aacu...