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» Nonlinear signal processor design: a building block approach
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IJCAI
1997
13 years 6 months ago
Evolvable Hardware for Generalized Neural Networks
This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scal...
Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani...
ASPDAC
2001
ACM
100views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Frank Gilbert, Alexander Worm, Norbert Wehn
DATE
2007
IEEE
125views Hardware» more  DATE 2007»
13 years 11 months ago
Simulation platform for UHF RFID
1 Developing modern integrated and embedded systems require well-designed processes to ensure flexibility and independency. These features are related to exchangeability of hardw...
Vojtech Derbek, Christian Steger, Reinhold Weiss, ...
ICCAD
2000
IEEE
159views Hardware» more  ICCAD 2000»
13 years 9 months ago
ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters
A tool is presented that gives a high-level estimation of the power consumed by an analog continuous-time OTA-C filter when given only high-level input parameters such as dynamic ...
Erik Lauwers, Georges G. E. Gielen
VLSID
2004
IEEE
209views VLSI» more  VLSID 2004»
14 years 5 months ago
An Architecture for Motion Estimation in the Transform Domain
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, ...