10 search results - page 2 / 2 » Novel binary linear programming for high performance clock m... |
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
- We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given ba...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
DAC
2009
ACM
13 years 8 months ago
2009
ACM
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...
IPPS
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper presents a technique for memory optimization for a class of computations that arises in the field of correlated electronic structure methods such as coupled cluster and...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
In this paper, a novel automatic approach for the concurrent topology and routing optimization that achieves a high quality network layout is proposed. This optimization is based ...