76 search results - page 2 / 16 » On Design and Analysis of a Feasible Network-on-Chip (NoC) A... |
NOCS
2007
IEEE
13 years 11 months ago
2007
IEEE
As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent...
CASES
2008
ACM
13 years 6 months ago
2008
ACM
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
IEEEHPCS
2010
13 years 3 months ago
2010
Network-on-chip (NoC) architectures adopted for Systemon-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, ...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Research studies have demonstrated the feasibility and advantages of Network-on-Chip (NoC) over traditional bus-based architectures but have not focused on compatibility communica...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival prob...