51 search results - page 3 / 11 » On Programmable Memory Built-In Self Test Architectures |
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...
VTS
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
ATS
2000
IEEE
13 years 9 months ago
2000
IEEE
We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
Abstract: We discuss the development of Built-In SelfTest (BIST) configurations that test all of the programmable logic and interconnect resources in the core of Xilinx 4000E, 4000...