21 search results - page 4 / 5 » On Retiming Synchronous Data-Flow Graphs |
DAM
2008
13 years 5 months ago
2008
In this paper, we address the following problem: given a synchronous digital circuit, is it possible to construct a new circuit computing the same function as the original one but...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
ICPP
1996
IEEE
13 years 10 months ago
1996
IEEE
Data locality and synchronization overhead are two important factors that affect the performance of applications on multiprocessors. Loop fusion is an effective way for reducing s...
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
ARC
2010
Springer
13 years 9 months ago
2010
Springer
Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on th...