11 search results - page 1 / 3 » On Test Set Preservation of Retimed Circuits |
DAC
1995
ACM
13 years 8 months ago
1995
ACM
DAC
1995
ACM
13 years 8 months ago
1995
ACM
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so chang...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
Abstract We propose a novel approach to preserve the synchronizing sequences of a circuit after retiming. The significance of this problem stems from the necessity of maintaining c...
ISPD
2004
ACM
13 years 10 months ago
2004
ACM
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
ASYNC
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...