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» On Test Set Preservation of Retimed Circuits
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ET
2010
122views more  ET 2010»
13 years 2 months ago
Fault Models for Quantum Mechanical Switching Networks
This work justifies several quantum gate level fault models and discusses the causal error mechanisms thwarting correct function. A quantum adaptation of the classical test set gen...
Jacob D. Biamonte, Jeff S. Allen, Marek A. Perkows...
TCAD
2008
96views more  TCAD 2008»
13 years 5 months ago
An Implicit Approach to Minimizing Range-Equivalent Circuits
Abstract--Simplifying a combinational circuit while preserving its range has a variety of applications, such as combinational equivalence checking and random simulation. Previous a...
Yung-Chih Chen, Chun-Yao Wang
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
13 years 10 months ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
JUCS
2007
95views more  JUCS 2007»
13 years 5 months ago
Using Place Invariants and Test Point Placement to Isolate Faults in Discrete Event Systems
: This paper describes a method of using Petri net P-invariants in system diagnosis. To model this process a net oriented fault classification is presented. Hence, the considered d...
Iwan Tabakow
DAC
2006
ACM
14 years 6 months ago
A new LP based incremental timing driven placement for high performance designs
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
Tao Luo, David Newmark, David Z. Pan