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ITC
2003
IEEE
120views Hardware» more  ITC 2003»
13 years 10 months ago
High Quality ATPG for Delay Defects
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...
Puneet Gupta, Michael S. Hsiao
DATE
2003
IEEE
102views Hardware» more  DATE 2003»
13 years 10 months ago
Non-Enumerative Path Delay Fault Diagnosis
The first non-enumerative framework for diagnosing path delay faults using zero suppressed binary decision diagrams is introduced. We show that fault free path delay faults with ...
Saravanan Padmanaban, Spyros Tragoudas
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
13 years 9 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler
VTS
2007
IEEE
95views Hardware» more  VTS 2007»
13 years 11 months ago
Delay Test Quality Evaluation Using Bounded Gate Delays
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
Soumitra Bose, Vishwani D. Agrawal
ASPDAC
2004
ACM
102views Hardware» more  ASPDAC 2004»
13 years 10 months ago
TranGen: a SAT-based ATPG for path-oriented transition faults
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...
Kai Yang, Kwang-Ting Cheng, Li-C. Wang