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» On reducing misspeculations in a pipelined scheduler
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INFOCOM
2012
IEEE
11 years 7 months ago
Robust multi-pipeline scheduling in low-duty-cycle wireless sensor networks
—Data collection is one of the major traffic pattern in wireless sensor networks, which requires regular source nodes to send data packets to a common sink node with limited end...
Yongle Cao, Shuo Guo, Tian He
JSS
2008
65views more  JSS 2008»
13 years 5 months ago
Process pipeline scheduling
This paper explores how process pipeline scheduling may become a viable strategy for executing workflows. It first details a workflow optimization and execution algorithm that redu...
Melissa Lemos, Marco A. Casanova, Antonio L. Furta...
IPPS
1998
IEEE
13 years 9 months ago
An Enhanced Co-Scheduling Method Using Reduced MS-State Diagrams
Instruction scheduling methods based on the construction of state diagrams (or automata) have been used for architectures involving deeply pipelined function units. However, the s...
Ramaswamy Govindarajan, N. S. S. Narasimha Rao, Er...
HPCA
2004
IEEE
14 years 5 months ago
Perceptron-Based Branch Confidence Estimation
Pipeline gating has been proposed for reducing wasted speculative execution due to branch mispredictions. As processors become deeper or wider, pipeline gating becomes more import...
Haitham Akkary, Srikanth T. Srinivasan, Rajendar K...
ASPDAC
2006
ACM
103views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Low area pipelined circuits by multi-clock cycle paths and clock scheduling
— A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algor...
Bakhtiar Affendi Rosdi, Atsushi Takahashi