418 search results - page 1 / 84 » On the Adders with Minimum Tests |
ATS
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper considers two types of n-bit adders, ripple carry adders and cascaded carry look-ahead adders, with minimum tests for stuck-at fault models. In the first part, we prese...
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
— This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detec...
VLSID
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4bits binary var...
IAJIT
2010
13 years 3 months ago
2010
: In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable a...
ISCAS
1995
IEEE
13 years 8 months ago
1995
IEEE
: Configurations of adders and registers, which are available in tnany datapaths, can be utilized to generate pattems and to compact test responses. Thispaper unalyzes tlie patiern...