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» On the Generation of Multiplexer Circuits for Pass Transisto...
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ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
13 years 9 months ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
13 years 8 months ago
Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
Randal E. Bryant
DSD
2007
IEEE
160views Hardware» more  DSD 2007»
13 years 11 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
ITC
1997
IEEE
80views Hardware» more  ITC 1997»
13 years 9 months ago
Scan Synthesis for One-Hot Signals
Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot sig...
Subhasish Mitra, LaNae J. Avra, Edward J. McCluske...
ASIAMS
2008
IEEE
13 years 11 months ago
High-Performance Carry Select Adder Using Fast All-One Finding Logic
A carry-select adder(CSA) can be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders to reduce the area and power but w...
Sun Yan, Zhang Xin, Jin Xi