31 search results - page 2 / 7 » On the Scalability of Routing Integrated Time Synchronizatio... |
CISIS
2009
IEEE
2009
IEEE
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
13 years 11 months ago
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
IPPS
2005
IEEE
13 years 10 months ago
2005
IEEE
In recent years, we have seen a dramatic increase in the use of data-centric distributed systems such as global grid infrastructures, sensor networks, network monitoring, and vari...
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
TCAD
2002
13 years 4 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
ADBIS
2009
Springer
13 years 9 months ago
2009
Springer
Scaling up web applications requires distribution of load across multiple application servers and across multiple database servers. Distributing load across multiple application se...