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» On the analysis of digital circuits with uncertain inputs
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ITC
1997
IEEE
107views Hardware» more  ITC 1997»
13 years 10 months ago
On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops
- An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops is introduced. Input jitter may be generated using one of two metho...
Benoît R. Veillette, Gordon W. Roberts
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 2 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
ASPDAC
2006
ACM
137views Hardware» more  ASPDAC 2006»
14 years 2 hour ago
Parameterized block-based non-gaussian statistical gate timing analysis
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
RSP
2003
IEEE
176views Control Systems» more  RSP 2003»
13 years 11 months ago
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, A...
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
13 years 11 months ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna