229 search results - page 1 / 46 » On-Chip Test Generation Using Linear Subspaces |
ETS
2006
IEEE
13 years 11 months ago
2006
IEEE
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
ATS
2009
IEEE
14 years 8 days ago
2009
IEEE
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measurin...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
ITC
1997
IEEE
13 years 9 months ago
1997
IEEE
- An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops is introduced. Input jitter may be generated using one of two metho...