48 search results - page 1 / 10 » On-Chip Test Infrastructure Design for Optimal Multi-Site Te... |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
MSE
2003
IEEE
13 years 10 months ago
2003
IEEE
A tool has been developed to automate the testing and grading of design projects implemented in reprogrammable hardware. The server allows multiple students to test circuits in FP...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two differe...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...