17 search results - page 1 / 4 » On-Chip Time Measurement Architecture with Femtosecond Timin... |
ETS
2006
IEEE
13 years 8 months ago
2006
IEEE
This paper presents a new on-chip time measurement architecture which is based on the Timeto-Digital Conversion (TDC) method that is capable of achieving a timing resolution of te...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Multi-channel waveform monitoring technique enhances built-in test and diagnostic capability of mixed-signal VLSI circuits. An 8-channel prototype system incorporates adaptive sam...
CODES
2003
IEEE
13 years 10 months ago
2003
IEEE
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
CODES
2009
IEEE
13 years 9 months ago
2009
IEEE
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...