9 search results - page 1 / 2 » On-chip interconnect modeling by wire duplication |
DAC
1999
ACM
14 years 6 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
HPCA
2003
IEEE
14 years 5 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...