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TVLSI
2008
197views more  TVLSI 2008»
13 years 5 months ago
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
Behnam Amelifard, Farzan Fallah, Massoud Pedram
ICCAD
2003
IEEE
149views Hardware» more  ICCAD 2003»
14 years 2 months ago
Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module L
This paper proposes an optimum methodology for assigning supply and threshold voltages to modules in a CMOS circuit such that the overall energy consumption is minimized for a giv...
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhij...
ISLPED
2003
ACM
142views Hardware» more  ISLPED 2003»
13 years 10 months ago
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
David Nguyen, Abhijit Davare, Michael Orshansky, D...
ISVLSI
2002
IEEE
174views VLSI» more  ISVLSI 2002»
13 years 10 months ago
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
Alice Wang, Anantha Chandrakasan, Stephen V. Koson...
SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
13 years 11 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann