20 search results - page 3 / 4 » Optimal Clock Period Clustering for Sequential Circuits with... |
DAC
2006
ACM
14 years 6 months ago
2006
ACM
In this paper we present a new efficient algorithm for retiming sequential circuits with edge-triggered registers under both setup and hold constraints. Compared with the previous...
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
Traditional approaches for sequential logic optimization include (1) explicit state-based techniques such as state minimization, (2) structural techniques such as retiming, and (3...
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
Clock skew scheduling has been effectively used to reduce the clock period of sequential circuits. However, this technique may become impractical if a different skew must be appli...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
In this paper, we propose an optimal gate sizing and clock skew optimization algorithm for globally sizing synchronous sequential circuits. The number of constraints and variables ...