261 search results - page 3 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
ITC
1998
IEEE
13 years 10 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
ITC
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
DELTA
2008
IEEE
14 years 7 days ago
2008
IEEE
Re-using embedded resources for implementing builtin self test mechanisms allows test cost reduction. In this paper we demonstrate how to implement costefficient built-in self tes...
DAC
1997
ACM
13 years 10 months ago
1997
ACM
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...
ATS
2000
IEEE
13 years 10 months ago
2000
IEEE