166 search results - page 1 / 34 » Optimal System-on-Chip Test Scheduling |
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
TPDS
2010
13 years 3 months ago
2010
—This paper presents the development and implementation of a multiprocessor system-on-chip solution for fast and real time simulations of complex and nonlinear wheel-rail contact...
MSE
2003
IEEE
13 years 10 months ago
2003
IEEE
A tool has been created for use in a design course to automate integration of new components into a SystemOn-Chip (SoC). Students used this tool to implement a complete SoC Intern...
DSD
2005
IEEE
13 years 10 months ago
2005
IEEE
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...