38 search results - page 2 / 8 » Optimal Transistor Tapering for High-Speed CMOS Circuits |
DAC
1994
ACM
13 years 9 months ago
1994
ACM
A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with ...
GECCO
2004
Springer
13 years 10 months ago
2004
Springer
This article summarizes two experiments utilizing building blocks to find analog electronic circuits on a CMOS Field Programmable Transistor Array (FPTA). The FPTA features 256 pr...
ISLPED
1995
ACM
13 years 8 months ago
1995
ACM
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
DATE
2005
IEEE
2005
IEEE
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
13 years 10 months ago
This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switc...
ICCD
2000
IEEE
14 years 1 months ago
2000
IEEE
This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating of the ground bounce is presen...