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» Optimal WCET-aware code selection for scratchpad memory
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EMSOFT
2010
Springer
13 years 2 months ago
Optimal WCET-aware code selection for scratchpad memory
We propose the first polynomial-time code selection algorithm for minimising the worst-case execution time of a nonnested loop executed on a fully pipelined processor that uses sc...
Hui Wu, Jingling Xue, Sridevan Parameswaran
ASPDAC
2006
ACM
126views Hardware» more  ASPDAC 2006»
13 years 10 months ago
A novel instruction scratchpad memory optimization method based on concomitance metric
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performance of certain embedded systems. Additionally, it has also been demonstrated tha...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
CGO
2005
IEEE
13 years 10 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
CODES
2008
IEEE
13 years 10 months ago
Scratchpad allocation for concurrent embedded software
Software-controlled scratchpad memory is increasingly employed in embedded systems as it offers better timing predictability compared to caches. Previous scratchpad allocation alg...
Vivy Suhendra, Abhik Roychoudhury, Tulika Mitra
DAC
2009
ACM
13 years 9 months ago
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
José Baiocchi, Bruce R. Childers