11 search results - page 1 / 3 » Optimal wire and transistor sizing for circuits with non-tre... |
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
TVLSI
2010
12 years 12 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
ISLPED
1995
ACM
13 years 8 months ago
1995
ACM
Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor lay...
TCAD
1998
13 years 4 months ago
1998
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
ISQED
2010
IEEE
14 years 3 days ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...