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    ICCAD
    1995
    IEEE
    79views Hardware» more  ICCAD 1995»
    Optimal wire sizing and buffer insertion for low power and a generalized delay model
    13 years 8 months ago
    Optimal wire sizing and buffer insertion for low power and a generalized delay model
    Download  www.cs.uic.edu
    John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
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    TVLSI
    2010
    149views Artificial Intelligence» more  TVLSI 2010»
    Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
    12 years 11 months ago
    Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
    Download  dropzone.tamu.edu
    Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
    Rupak Samanta, Jiang Hu, Peng Li
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    VLSID
    2003
    IEEE
    183views VLSI» more  VLSID 2003»
    Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
    14 years 5 months ago
    Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
    Download  www.ee.iitb.ac.in
    We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...
    Vani Prasad, Madhav P. Desai
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    GLVLSI
    2003
    IEEE
    157views VLSI» more  GLVLSI 2003»
    Optimum wire sizing of RLC interconnect with repeaters
    13 years 10 months ago
    Optimum wire sizing of RLC interconnect with repeaters
    Download  www.ece.rochester.edu
    Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive and can affect signal behavior. The line inductance should therefore be co...
    Magdy A. El-Moursy, Eby G. Friedman
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    ISVLSI
    2008
    IEEE
    142views VLSI» more  ISVLSI 2008»
    A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing
    13 years 11 months ago
    A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing
    Download  www.csee.usf.edu
    In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation e...
    Venkataraman Mahalingam, Nagarajan Ranganathan
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