70 search results - page 3 / 14 » Optimization of combinational and sequential logic circuits ... |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
ICCAD
2008
IEEE
13 years 11 months ago
2008
IEEE
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
APCCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
— A data driven approach to design and optimization of low power combinational multipliers is presented. This technique depends on signal gating to avoid un-necessary computation...
ISLPED
2009
ACM
13 years 11 months ago
2009
ACM
This paper explores the use of serial circuits for ultra-low-power sub-threshold systems. A serial system leads to a smaller design and higher utilization, yielding 40% active ene...