194 search results - page 2 / 39 » Optimizing Technology Mapping for FPGAs Using CAMs |
DAC
2005
ACM
14 years 6 months ago
2005
ACM
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
FPGA
2008
ACM
13 years 7 months ago
2008
ACM
This paper presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the ite...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
FPL
2000
Springer
13 years 9 months ago
2000
Springer
As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation h...
17
Voted
IROS
2007
IEEE
13 years 11 months ago
2007
IEEE
— In this paper, we address the problem of learning 3D maps of the environment using a cheap sensor setup which consists of two standard web cams and a low cost inertial measurem...