19 search results - page 3 / 4 » Optimum wire sizing of RLC interconnect with repeaters |
DAC
2004
ACM
13 years 8 months ago
2004
ACM
In this paper, we investigate the problem of repeater insertion for low power under a given timing budget. We propose a novel repeater insertion algorithm to compute the optimal r...
VLSISP
2008
13 years 4 months ago
2008
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
DSD
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract—Pulse-based data transmission has been demonstrated as a power-saving and high performance alternative to level-based signalling over global distances. Key to its correc...