22 search results - page 1 / 5 » Output Prediction Logic: A High-Performance CMOS Design Tech... |
ICCD
2000
IEEE
13 years 9 months ago
2000
IEEE
ARVLSI
2001
IEEE
13 years 8 months ago
2001
IEEE
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various...
DAC
1994
ACM
13 years 9 months ago
1994
ACM
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...