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ASPDAC
2005
ACM
101views Hardware» more  ASPDAC 2005»
13 years 8 months ago
A wideband hierarchical circuit reduction for massively coupled interconnects
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
DATE
2002
IEEE
87views Hardware» more  DATE 2002»
13 years 11 months ago
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods
We present a new passive model reduction algorithm based on the Laguerre expansion of the time response of interconnect networks. We derive expressions for the Laguerre coefficie...
Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok...
DATE
2010
IEEE
124views Hardware» more  DATE 2010»
13 years 11 months ago
On the construction of guaranteed passive macromodels for high-speed channels
Abstract—This paper describes a robust and accurate blackbox macromodeling technique, in which the constitutive equations combine both closed-form delay operators and low-order r...
Alessandro Chinea, Stefano Grivet-Talocia, Dirk De...
DAC
2000
ACM
13 years 10 months ago
Passive model order reduction of multiport distributed interconnects
Signal integrity analysis has become imperative for high-speed designs. In this paper, we present a new technique to advance Krylov-space based passive model-reduction algorithms ...
Emad Gad, Anestis Dounavis, Michel S. Nakhla, Rama...
ICCAD
2007
IEEE
115views Hardware» more  ICCAD 2007»
14 years 3 months ago
Parameterized model order reduction via a two-directional Arnoldi process
Abstract—This paper presents a multiparameter momentmatching based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi pro...
Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng