Sciweavers

257 search results - page 1 / 52
» Packet-Based Input Test Data Compression Techniques
Sort
View
ITC
2002
IEEE
83views Hardware» more  ITC 2002»
13 years 9 months ago
Packet-Based Input Test Data Compression Techniques
1 This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The techni...
Erik H. Volkerink, Ajay Khoche, Subhasish Mitra
ET
2002
111views more  ET 2002»
13 years 4 months ago
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional co...
Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wun...
DATE
2002
IEEE
135views Hardware» more  DATE 2002»
13 years 9 months ago
Reducing Test Application Time Through Test Data Mutation Encoding
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...
Sherief Reda, Alex Orailoglu
ICCD
2003
IEEE
130views Hardware» more  ICCD 2003»
14 years 1 months ago
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume
This paper presents a pinpoint test set relaxation method for test compression that maximally derives the capability of a run-length encoding technique such as Golomb coding or fr...
Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Cha...
DATE
2002
IEEE
103views Hardware» more  DATE 2002»
13 years 9 months ago
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression
We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...
Anshuman Chandra, Krishnendu Chakrabarty