284 search results - page 3 / 57 » Parallel buffers for chip multiprocessors |
ISCAS
2008
IEEE
14 years 4 days ago
2008
IEEE
— A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, th...
ISCA
2003
IEEE
13 years 11 months ago
2003
IEEE
We describe the Java runtime parallelizing machine (Jrpm), a complete system for parallelizing sequential programs automatically. Jrpm is based on a chip multiprocessor (CMP) with...
ISSS
2002
IEEE
13 years 10 months ago
2002
IEEE
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Design space exploration of multiprocessors on chip requires both automatic performance analysis techniques and efficient multiprocessors configuration performance evaluation. Pr...