139 search results - page 27 / 28 » Parallel external memory graph algorithms |
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
This paper considers the role of performance and area estimates from behavioral synthesis in design space exploration. We have developed a compilation system that automatically ma...
LCTRTS
2007
Springer
13 years 11 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
WWW
2007
ACM
14 years 5 months ago
2007
ACM
A minimal perfect function maps a static set of keys on to the range of integers {0,1,2, ... , - 1}. We present a scalable high performance algorithm based on random graphs for ...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network a...