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ICPP
2007
IEEE
13 years 11 months ago
Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors
Ever-increasing memory footprint of applications and increasing mainstream popularity of shared memory parallel computing motivate us to explore memory compression potential in di...
Lakshmana Rao Vittanala, Mainak Chaudhuri
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
13 years 9 months ago
A portable and extendible testbed for distributed logic simulation
A exible test environment is presented that allows for dierent methods of parallelizing discrete event simulation to be evaluated in a uniform environment. The testbed is portabl...
Peter Luksch
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
13 years 9 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
DATE
2009
IEEE
172views Hardware» more  DATE 2009»
14 years 1 days ago
On bounding response times under software transactional memory in distributed multiprocessor real-time systems
We consider multiprocessor distributed real-time systems where concurrency control is managed using software transactional memory (or STM). For such a system, we propose an algori...
Sherif Fadel Fahmy, Binoy Ravindran, E. Douglas Je...
IPPS
2003
IEEE
13 years 10 months ago
Active Memory Techniques for ccNUMA Multiprocessors
Our recent work on uniprocessor and single-node multiprocessor (SMP) active memory systems uses address remapping techniques in conjunction with extended cache coherence protocols...
Daehyun Kim, Mainak Chaudhuri, Mark Heinrich