Ever-increasing memory footprint of applications and increasing mainstream popularity of shared memory parallel computing motivate us to explore memory compression potential in di...
A
exible test environment is presented that allows for dierent methods of parallelizing discrete event simulation to be evaluated in a uniform environment. The testbed is portabl...
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
We consider multiprocessor distributed real-time systems where concurrency control is managed using software transactional memory (or STM). For such a system, we propose an algori...
Sherif Fadel Fahmy, Binoy Ravindran, E. Douglas Je...
Our recent work on uniprocessor and single-node multiprocessor (SMP) active memory systems uses address remapping techniques in conjunction with extended cache coherence protocols...