14 search results - page 2 / 3 » Parallel-pipelined architecture for 2-D ICT VLSI implementat... |
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
— a form-preserving 2D z-domain helix transform is proposed for the synthesis of computable practical-BIBO stable 2D recursive filters computed over uniformly-spaced circular inp...
APCCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
— We propose a VLSI architecture for the single-chip realization of 2D spatio-temporal IIR digital filters, consisting of a meshed connection of concurrent identical vector-proce...
FCCM
2005
IEEE
13 years 10 months ago
2005
IEEE
In many image processing applications, fast convolution of an image with a large 2D filter is required. Field Programable Gate Arrays (FPGAs) are often used to achieve this goal ...
IJNS
2000
13 years 5 months ago
2000
An architecture is proposed for the realization of real-time edge-extraction filtering operation in an Address-Event-Representation (AER) vision system. Furthermore, the approach ...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a VLSI Architecture to implement the forward and inverse 2-D Discrete Wavelet Transform (FDWT/IDWT), to compress medical images for storage and retrieval. Loss...