151 search results - page 30 / 31 » Parallelizing while loops for multiprocessor systems |
SOSP
1997
ACM
13 years 7 months ago
1997
ACM
Low-latency remote-write networks, such as DEC’s Memory Channel, provide the possibility of transparent, inexpensive, large-scale shared-memory parallel computing on clusters of...
PPL
2008
13 years 5 months ago
2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
USENIX
2007
13 years 8 months ago
2007
Data Structure Abstractions for Asynchronous Web Applications Daniel S. Myers MIT CSAIL Jennifer N. Carlisle MIT CSAIL James A. Cowling MIT CSAIL Barbara H. Liskov MIT CSAIL The c...
IEEEPACT
2006
IEEE
13 years 11 months ago
2006
IEEE
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
HPCA
2009
IEEE
14 years 6 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...