23 search results - page 5 / 5 » Partial scan delay fault testing of asynchronous circuits |
DAC
2006
ACM
14 years 5 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
ATS
1996
IEEE
13 years 9 months ago
1996
IEEE
In this paper, we present a novel and efticient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method an...
VTS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...