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    FPGA
    1997
    ACM
    120views FPGA» more  FPGA 1997»
    Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping
    13 years 9 months ago
    Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping
    Download  cadlab.cs.ucla.edu
    In this paper, we give a necessary and sufficient condition for the existence of partially-dependent functional decomposition and develop new algorithms to compute such decomposi...
    Jason Cong, Yean-Yow Hwang
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    DAC
    1998
    ACM
    138views Computer Architecture» more  DAC 1998»
    Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis
    13 years 9 months ago
    Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis
    Download  www.cs.york.ac.uk
    Recently, functional decomposition has been adopted for LUT based FPGA technology mapping with good results. In this paper, we propose a novel method for functional multipleoutput...
    Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Hu...
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    DAC
    1995
    ACM
    124views Computer Architecture» more  DAC 1995»
    A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis
    13 years 8 months ago
    A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis
    Download  www.cecs.uci.edu
    —In this paper, we present an algorithm for finding a good Ashenhurst decomposition of a switching function. Most current methods for performing this type of decomposition are ba...
    Ted Stanion, Carl Sechen
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    ICCAD
    1993
    IEEE
    134views Hardware» more  ICCAD 1993»
    Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
    13 years 9 months ago
    Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
    Download  cadlab.cs.ucla.edu
    In this paper, we present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, na...
    Jason Cong, Yuzheng Ding
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    ICCAD
    2007
    IEEE
    164views Hardware» more  ICCAD 2007»
    Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
    14 years 1 months ago
    Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
    Download  www.ee.ucla.edu
    — Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
    Yu Hu, Satyaki Das, Steven Trimberger, Lei He
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