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FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
12 years 9 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
CODES
2006
IEEE
13 years 11 months ago
The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications
Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resourcerelated constraints. As this complexity increases, th...
Dong-Ik Ko, Shuvra S. Bhattacharyya
ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
13 years 9 months ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...
RSP
2003
IEEE
176views Control Systems» more  RSP 2003»
13 years 10 months ago
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, A...