The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications

Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resourcerelated constraints. As this complexity increases, the application of single-chip multiprocessor technology is attractive. To address the challenges of mapping image processing applications onto embedded multiprocessor platforms, this paper presents a novel data structure called the pipeline decomposition tree (PDT), and an associated scheduling framework, which we refer to as PDT scheduling. PDT scheduling exploits both heterogeneous data parallelism and task-level parallelism, which are important considerations for scheduling image processing applications. This paper develops the PDT representation for system synthesis, and presents methods using the PDT to derive customized pipelined architectures that are streamlined for the given implementation constraints. Categories and Subject Descriptors C.3 [Real-time embedded systems] General Terms Design Keywords De...

• Type: Conference
• Year: 2006
• Where: CODES
• Authors: Dong-Ik Ko, Shuvra S. Bhattacharyya
• Keywords: CODES 2006, Hardware-Software Codesign, Image Processing, Image Processing Applications, PDT Scheduling