19 search results - page 3 / 4 » Path Delay Test Generation for Domino Logic Circuits in the ... |
DAC
2005
ACM
13 years 8 months ago
2005
ACM
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
VTS
1999
IEEE
13 years 10 months ago
1999
IEEE
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is propose...
ATS
2000
IEEE
13 years 10 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
VLSID
1996
IEEE
13 years 10 months ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
ICCAD
1999
IEEE
13 years 10 months ago
1999
IEEE
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...