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DAC
2002
ACM
14 years 6 months ago
Analysis of power consumption on switch fabrics in network routers
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, inte...
Terry Tao Ye, Giovanni De Micheli, Luca Benini
WEA
2005
Springer
120views Algorithms» more  WEA 2005»
13 years 11 months ago
Distilling Router Data Analysis for Faster and Simpler Dynamic IP Lookup Algorithms
Abstract. We consider the problem of fast IP address lookup in the forwarding engines of Internet routers. We analyze over 2400 public snapshots of routing tables collected over ...
Filippo Geraci, Roberto Grossi
ICC
2007
IEEE
138views Communications» more  ICC 2007»
14 years 3 days ago
Scalable Router Memory Architecture Based on Inter-leaved DRAM: Analysis and Numerical Studies
1  Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
Feng Wang, Mounir Hamdi
AINA
2007
IEEE
14 years 4 days ago
Sizing Router Buffers for Large-Scale TCP/IP Networks
— We investigate the validity of reducing router buffer size in a large-scale network that includes both core networks and edge networks. We first devise a novel mathematical an...
Hiroyuki Hisamatsu, Go Hasegawa, Masayuki Murata
DAC
2005
ACM
14 years 6 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...