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» Performance Evaluation of Tiling for the Register Level
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TMC
2008
192views more  TMC 2008»
13 years 5 months ago
A Bidding Algorithm for Optimized Utility-Based Resource Allocation in Ad Hoc Networks
Abstract-- This article proposes a scheme for bandwidth allocation in wireless ad hoc networks. The quality of service (QoS) levels for each end-to-end flow are expressed using a r...
Calin Curescu, Simin Nadjm-Tehrani
TCAD
2008
183views more  TCAD 2008»
13 years 5 months ago
Systematic and Automated Multiprocessor System Design, Programming, and Implementation
Abstract--For modern embedded systems in the realm of highthroughput multimedia, imaging, and signal processing, the complexity of embedded applications has reached a point where t...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
12 years 9 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
13 years 12 months ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li
PLDI
2005
ACM
13 years 11 months ago
Pin: building customized program analysis tools with dynamic instrumentation
Robust and powerful software instrumentation tools are essential for program analysis tasks such as profiling, performance evaluation, and bug detection. To meet this need, we ha...
Chi-Keung Luk, Robert S. Cohn, Robert Muth, Harish...