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» Performance Predictions for Speculative, Synchronous, VLSI L...
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GLVLSI
2007
IEEE
173views VLSI» more  GLVLSI 2007»
13 years 5 months ago
Modeling and estimating leakage current in series-parallel CMOS networks
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...
Paulo F. Butzen, André Inácio Reis, ...
GLVLSI
2005
IEEE
152views VLSI» more  GLVLSI 2005»
13 years 11 months ago
A high speed and leakage-tolerant domino logic for high fan-in gates
Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in ...
Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peirav...
GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
13 years 7 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang