Modeling and estimating leakage current in series-parallel CMOS networks

This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networks, ignored by previous works, is considered in static current analysis. Both contributions present significant influence in the logic circuit leakage prediction when CMOS complex gates are extensively used. The proposed leakage model has been validated through electrical simulations, taking into account a 130nm CMOS technology, with good correlation of the results. Categories and Subject Descriptors B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids General Terms Design, Performance

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
• Keywords: Circuit Leakage Prediction, CMOS, GLVLSI 2007, Series-parallel Cmos Networks, VLSI