1370 search results - page 2 / 274 » Performance analysis and optimization of latency insensitive... |
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
NOCS
2008
IEEE
13 years 12 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
—Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations h...
ENTCS
2006
13 years 5 months ago
2006
Back-pressure is a logical mechanism to control the flow of information on a communication channel of a latency-insensitive system (LIS) while guaranteeing that no packet is lost....
ENTCS
2008
13 years 5 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...