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CF
2010
ACM
13 years 10 months ago
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cach
As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to des...
Pierre Michaud, Yiannakis Sazeides, André S...
ISSS
2002
IEEE
136views Hardware» more  ISSS 2002»
13 years 10 months ago
Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors
This paper presents a new technique for global energy optimization through coordinated functional partitioning and speed selection for embedded processors interconnected by a high...
Nader Bagherzadeh, Pai H. Chou, Jinfeng Liu
ISCA
2007
IEEE
113views Hardware» more  ISCA 2007»
13 years 11 months ago
Thermal modeling and management of DRAM memory systems
With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management (DTM) a...
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard Da...
DAC
2009
ACM
14 years 6 months ago
Dynamic thermal management via architectural adaptation
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...
Ramkumar Jayaseelan, Tulika Mitra
ASPDAC
2008
ACM
150views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Bus-aware microarchitectural floorplanning
Abstract-- In this paper we present the first bus-aware microarchitectural floorplanning. Our goal is to study the impact of bus routability on other important floorplanning object...
Dae Hyun Kim, Sung Kyu Lim