119 search results - page 2 / 24 » Performance optimization of elastic systems using buffer res... |
DAC
1998
ACM
13 years 9 months ago
1998
ACM
Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in gl...
ICCAD
2003
IEEE
13 years 11 months ago
2003
IEEE
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
Abstract— As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
Most existing buffering algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches...
ICCAD
2002
IEEE
13 years 10 months ago
2002
IEEE
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-c...